1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly, to a circuit for driving a nonvolatile ferroelectric memory.
2. Background of the Related Art
A ferroelectric random access memory (FRAM) has a data processing speed as fast as a DRAM and conserves data even after the power is turned off. The FRAM includes capacitors similiar to the DRAM, but the capacitors have a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not lost even after eliminating an electric field applied thereto.
FIG. 1A illustrates a general hysteresis loop of a ferroelectric substance, and FIG. 1B illustrates a construction of a unit capacitor in a background art ferroelectric memory. As shown in the hysteresis loop in FIG. 1A, a polarization induced by an electric field does not vanish, but remains at a certain portion (xe2x80x9cdxe2x80x9d or xe2x80x9caxe2x80x9d state) even after the electric field is cleared due to an existence of a spontaneous polarization. These xe2x80x9cdxe2x80x9d and xe2x80x9caxe2x80x9d states may be matched to binary values of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d for use as a memory cell. Referring to FIG. 1B, the state in which a positive voltage is applied to a node 1 is a xe2x80x9ccxe2x80x9d state in FIG. 1A, the state in which no voltage is applied thereafter to the node 1 is a xe2x80x9cdxe2x80x9d state. Opposite to this, if a negative voltage is applied to the node 1, the state moves from the xe2x80x9cdxe2x80x9d to an xe2x80x9cfxe2x80x9d state. If no voltage is applied to the node 1, thereafter the state moves to an xe2x80x9caxe2x80x9d state. If a positive voltage is applied again, the states moves the xe2x80x9ccxe2x80x9d state via the xe2x80x9cbxe2x80x9d state. At the end, even if there is no voltage applied on both ends of a capacitor, a data can be stored in stable state of xe2x80x9caxe2x80x9d and xe2x80x9cdxe2x80x9d. On the hysteresis loop, xe2x80x9ccxe2x80x9d and xe2x80x9cdxe2x80x9d states correspond to a binary logic value of xe2x80x9c1xe2x80x9d, and xe2x80x9caxe2x80x9d and xe2x80x9cfxe2x80x9d states correspond to a binary logic value xe2x80x9c0xe2x80x9d.
In reading a data from the capacitor, the xe2x80x9cdxe2x80x9d state is destroyed to read the data stored in the capacitor. In a background art, a sense amplifier is used for reading a data using a voltage generated in a reference voltage generator and a voltage generated in a main cell array. In a ferroelectric reference cell, two modes of xe2x80x9c1xe2x80x9d polarity and xe2x80x9c0xe2x80x9d polarity are used for generating a reference voltage on a reference bitline. Accordingly, the sense amplifier compares a bitline voltage on a main cell and a reference bitline voltage on a reference cell, to read information in the main cell. By rewriting the read data within the same cycle, the destroyed data can be recovered.
FIG. 2 illustrates a unit cell of a background art ferroelectric memory. The unit cell of a background art ferroelectric memory is provided with a bitline B/L formed in a direction, a wordline W/L formed in a direction crossing the bitline, a plateline P/L formed in the same direction with the wordline spaced therefrom, a transistor T1 having a gate connected to the wordline and a source connected to the bitline, and a ferroelectric capacitor FC1 having a first terminal connected to a drain of the transistor T1 and a second terminal connected to the plateline.
FIGS. 3a and 3b together illustrate a circuit for driving the background art one transistor/one capacitor (1T/1C) ferroelectric memory of FIG. 2. A reference voltage generating part 1 generates a reference voltage, and a reference voltage stabilizing part 2 having a plurality of transistors Q1xcx9cQ4 and a capacitor C1 stabilizes a reference voltage on two adjacent bitlines B1 and B2 because the reference voltage from the reference voltage generating part 1 can not be provided to a sense amplifier directly. A first reference voltage storage part 3 having a plurality of transistors Q6xcx9cQ7 and capacitors C2xcx9cC3 stores a logic value xe2x80x9c0xe2x80x9d in adjacent bit lines. A first equalizing part 4 having a transistor Q5 equalizes adjacent two bitlines.
A first main cell array part 5 connected to wordlines W/L and platelines P/L different from one another stores data, and a first sense amplifier part 6 having a plurality of transistors Q10xcx9cQ15 and P-sense amplifiers PSA senses a data in a cell selected by the wordline from the plurality of cells in the main cell array part 5. A second main cell array part 7 connected to wordlines and platelines different from one another stores data, and a second reference voltage storage part 8 having a plurality of transistors Qxcx9cQ29 and capacitors C9xcx9cC10 stores a logic value xe2x80x9c1xe2x80x9d and a logic value xe2x80x9c0xe2x80x9d in adjacent bit lines. A second sense amlifier part 9 having a plurality of transistors Q15xcx9cQ24 and N-sense amplifiers NSA senses a data in the second main cell array part 7.
FIG. 4 illustrates a timing diagram showing a write mode operation of the background art ferroelectric memory. First, when a chip enable signal CSBpad received externally is enabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d and a write enable signal WEBpad also transits from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d, the write mode is started. An address decoding is started in the write mode, to transit a pulse applied to a selected wordline from xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d to a selected cell. In an interval where the wordline is thus held at xe2x80x9chighxe2x80x9d, a corresponding plateline P/L is applied of a xe2x80x9chighxe2x80x9d signal for an interval and a xe2x80x9clowxe2x80x9d signal for an interval in a sequence and a corresponding bitline is applied of a xe2x80x9chighxe2x80x9d or xe2x80x9clowxe2x80x9d signal synchronous to the write enable signal, for writing a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d on the selected cell. In other words, if a signal applied to the plateline is xe2x80x9clowxe2x80x9d in an interval where the bitline is applied of a xe2x80x9chighxe2x80x9d signal and the wordline is applied of a xe2x80x9chighxe2x80x9d signal, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor. If a signal applied to the plateline is xe2x80x9chighxe2x80x9d and the bitline is applied of a xe2x80x9clowxe2x80x9d signal, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor.
The operation for reading a data stored in a cell with the write mode operation will be explained with reference to FIG. 5. When the chip enable signal CSBpad is enabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d externally, all bitlines are equalized to xe2x80x9clowxe2x80x9d by an equalizer signal before selection of a corresponding wordline. As shown in FIGS. 3a and 3b, when a xe2x80x9chighxe2x80x9d signal is applied to the equalizer part 4 and a xe2x80x9chighxe2x80x9d signal is applied to transistors Q18 and Q19, grounding the bitlines through transistors Q18 and Q19, the bitlines are equalized to a low voltage Vss. The transistors Q5, Q18 and Q19 are turned off, disabling corresponding bitlines, and address is decoded for transiting a corresponding wordline from xe2x80x9clowxe2x80x9d to xe2x80x9chighxe2x80x9d, to select a corresponding cell. Then, a xe2x80x9chighxe2x80x9d signal is applied to a plateline of the selected cell, to cancel data corresponding to a logic value xe2x80x9c1xe2x80x9d stored in an FRAM. If the FRAM is in storage of a logic value xe2x80x9c0xe2x80x9d, a data corresponding to it will not be canceled. A cell with a canceled data and a cell with a data not canceled provide signals different from each other according to the aforementioned hysteresis loop principle. Data provided through the bitline is sensed by the sense amplifier of a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
That is, referring to FIG. 1, since the case of a canceled data is a case when a state is changed from xe2x80x9cdxe2x80x9d to xe2x80x9cfxe2x80x9d, and the case of a data not canceled is a case when a state is changed from xe2x80x9caxe2x80x9d to xe2x80x9cfxe2x80x9d, if the sense amplifier is enable after a certain time, in the case of the canceled data, the data is amplified to provide a logic value xe2x80x9c1xe2x80x9d, and, in the case of the data not canceled, the data is amplified to provide a logic value xe2x80x9c0xe2x80x9d. After the sense amplifier amplifies and provides a signal, since the cell should be recovered of an original data, during xe2x80x9chighxe2x80x9d is applied to a corresponding line, the plateline is disabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d. However, in the background art 1T/1C ferroelectric memory, in which the reference cell is operative more than the main memory cell in data input and output operations, the reference cell degrades rapidly.
Accordingly, the background art ferroelectric memory and a circuit for driving the same have various problems. Since one reference cell of a ferroelectric substance of which ferroelectric property is not fully assured is provided for a few hundreds of main memories for use in reading operation, requiring much more operation of the reference cell, the reference cell is involved in a rapid degradation of the ferroelectric property, causing instability of the reference voltage and subsequent degradation of device operation performance and life time.
Accordingly, the present invention is directed a circuit for driving a nonvolatile ferroelectric memory that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for driving a nonvolatile ferroelectric memory which improves device operation performance and life time.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the circuit for driving a nonvolatile ferroelectric memory, the memory having a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines and a reference bitline on one side of the plurality of bitlines, includes a cell array having a plural times of repetitive arrangement of the plurality of bitlines and the reference bitline on one side thereof, a sense amplifier array having a plurality of sense amplifiers for sensing data on the bitlines and the reference bitlines in the cell array, a wordline and plateline driver for selective application of driving signals to the wordlines and the platelines, and a switching part for selective turning on/off of the bitlines, the reference bitlines, and the input/output nodes on the sense amplifier array, whereby improving a chip operation performance and a lifetime.
The present invention can be achieved in parts or in a whole by a ferroelectric memory having a plurality of bitlines, a plurality of wordlines and plate lines formed in a direction crossing the bitlines, and a reference bitline on one side of the plurality of bitlines, the circuit comprising a main cell array having a plurality of main cells, each main cell being coupled to corresponding wordline, plateline and bitline; a reference cell array having a plurality of reference cells, each reference cell being coupled to corresponding wordline, plateline and reference bitline; a sense amplifier array having a plurality of sense amplifiers for sensing data on the bitlines and the reference bitlines; a driver for providing driving signals to the wordlines and the platelines; and a switching unit for selective connection of the bitlines and the reference bitline to input/output nodes and reference nodes, respectively, on the sense amplifier array.
The present invention can be achieved in parts or in a whole by a nonvolatile ferroelectric memory, comprising: a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at a corresponding crossing point of the bitlines with the wordlines and the platelines; a first reference cell block on one side of the first main cell block, the first reference cell block having a reference bitline formed in a direction crossing the wordlines and the platelines and a reference cell on a corresponding crossing point of the reference bitline with the wordlines and the platelines; a first sense amplifier block having a plurality of sense amplifiers each sense amplifier having a bitline input/output node connected to the bitline for sensing a data on a corresponding bitline and a reference bitline input/output node connected to the reference bitline for sensing a data on the reference bitline; a first switching unit for selective connection of the bitline to the bitline input/output node on each of the sense amplifiers in response to a first control signal; a second switching unit for selective connection of the reference bitline to the reference input/output node on each of the sense amplifiers in response to a second control signal; and a pull-up transistor for pulling-up a level of the reference bitline to a level of a power supply voltage in response to a third control signal.
The present invention can be achieved in parts or in a whole by a nonvolatile ferroelectric memory comprising: a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at a corresponding crossing point of the bitlines with the wordlines and the platelines; a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell on a corresponding crossing point of the first and second reference bitlines with the wordlines and the platelines; a first lower sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an odd numbered bitline for sensing a data on the odd numbered bitline and a reference bitline input/output node connected to the first reference bitline for sensing a data on the first reference bitline; a first upper sense amplifier block having a plurality of sense amplifiers, each sense amplifier with a bitline input/output node connected to an even numbered bitline for sensing a data on the even numbered bitline and a reference bitline input/output node connected to the second reference bitline for sensing a data on the second reference bitline; a first switching unit for selective connection of the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first lower sense amplifier block; a second switching unit for selective connection of the reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first lower sense amplifier block; a third switching unit for selective connection of the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first upper sense amplifier block; a fourth switching unit for selective connection of the reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first upper sense amplifier block; and first and second pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively.
The present invention can be achieved in parts or in a whole by a nonvolatile ferroelectric memory comprising: a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at every second crossing point of the bitlines with the wordlines and the platelines; a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell at every second crossing point of the first and second reference bitlines with the wordlines and the platelines; a first sense amplifier block having a plurality of sense amplifiers, each sense amplifier having a bitline input/output node connected to a bitline in the first main cell block and an odd numbered reference bitline input/output node connected to the first reference bitline and an even numbered reference bitline input/output node connected to the second reference bitline; a first switching unit for selective connection of the bitlines to the bitline input/output nodes on the sense amplifiers; a second switching unit for selective connection of the first and second reference bitlines to the corresponding even and odd reference bitline input/output nodes on the sense amplifiers; and pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively.
The present invention can be achieved in parts or in a whole by a nonvolatile ferroelectric memory comprising: a first main cell block having a plurality of bitlines, a plurality of wordlines and platelines formed in a direction crossing the bitlines, and a main cell at every second crossing point of the bitlines with the wordlines and the platelines; a first reference cell block on one side of the first main cell block, the first reference cell block having first and second reference bitlines formed in a direction crossing the wordlines and the platelines and a reference cell on every second crossing point of the first and second reference bitlines with the wordlines and the platelines; a first lower sense amplifier block having a plurality of sense amplifiers, each sense amplifier having a bitline input/output node connected to an odd numbered bitline for sensing a data on the odd numbered bitline and a reference bitline input/output node connected to the first reference bitline for sensing a data on the first reference bitline; a first upper sense amplifier block having a plurality of sense amplifiers, each sense amplifier having a bitline input/output node connected to an even numbered bitline for sensing a data on the even numbered bitline and a reference bitline input/output node connected to the second reference bitline for sensing a data on the second reference bitline; a first switching unit for selective connection of the odd numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first lower sense amplifier block; a second switching unit for selective connection of the first reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first lower sense amplifier block; a third switching unit for selective connection of the even numbered bitlines to the bitline input/output nodes on the sense amplifiers in the first upper sense amplifier block; a fourth switching unit for selective connection of the second reference bitline to the reference bitline input/output node on each of the sense amplifiers in the first upper sense amplifier block; and pull-up transistors for pulling-up levels of the first and second reference bitlines to a level of a power supply voltage, respectively.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.